1. Field of the Invention
The invention relates to the field of electrically programmable and electrically erasable memory cells particularly those employing floating gates.
2. Prior Art
For many years now, metal-oxide-semiconductor (MOS) technology has been used to fabricate electrically programmable read-only memories (EPROMs). Many of these cells employ floating gates, that is, generally polysilicon members completely surrounded by an insulator. Electrical charge is transferred into the floating gate through a variety of mechanisms such as avalanche injection, channel injection, Fowler-Nordheim tunnelling, hot electron injection from the substrate, etc. A variety of phenomena have been used to remove charge including exposing the memory to ultraviolet radiation. Commercial EPROMs with floating gates first used avalanche injection to charge the floating gate; in second generation memories channel injection is used for programming. These memories are currently erased by exposure to ultraviolet radiation.
Commercial electrically programmable and electrically erasable memories (EEPROMs) have generally used a thin oxide region to tunnel charge into and from a floating gate. In a typical memory, a two transistor cell is used. See, for instance, U.S. Pat. No. 4,203,158 for a discussion of such cells and U.S. Pat. No. 4,266,283 for a discussion of related circuitry. These EEPROM cells do not lend themselves to being reduced in substrate area as do the EPROM cells. Thus, while relatively dense EPROMs are currently available (e.g., 256K) the EEPROMs are not available in as dense arrays.
Ideally, an EEPROM cell is needed which lends itself to small scale geometries (below the 50 micro m.sup.2 densities which is projected to be the best achievable for current cells). Importantly, the EEPROM should operate from a 5 volt potential; that is, the current needed for high voltage programming and erasing should be provided by a charge pumping circuit located on the chips.
One attempt to provide higher density, low voltage EPROM and EEPROM cells is shown in U.S. Pat. No. 4,432,075 and U.S. Pat. No. 4,577,295. A single source of hot electrons is shared by a number of cells for programming. This provides the advantages of not requiring the larger geometries used to assure channel injection. This technology has not yet been commercialized since programming appears to be slow.
A single transistor EEPROM cell which uses channel injection for programming a floating gate and tunneling for discharging the gate is described in copending application, Ser. No. 892,446, filed Aug. 4, 1986, and entitled LOW VOLTAGE EEPROM CELL. This application is assigned to the assignee of the present application. The advantages of this cell are its small size, its ability to be reduced in scale and the fact that it is a true "one-transistor" electrically programmable and electrically erasable cell. Moreover, this cell is compatible with conventional UV-erasable EPROM processing.
There are, however, some potential problems with the memory cell mentioned in the preceding paragraph. First, the threshold of the cell may become negative (i.e., depletion like) after erasing. The negative threshold voltage after erasing can disable an entire column line in an array. Secondly, the limited gate diode breakdown voltage at the source region (the node where erase voltage is applied) can be troublesome. The limited gated diode breakdown voltage may lead to potential reliability problems, as well as difficulty in providing an adequate charge pump circuit.
As will be seen the present invention provides a memory cell which overcomes the problems, yet is realizable in a high density array.
Other prior art known to Applicant is an article entitled "EPROM Cell with High Gate Injection Efficiency", presented at the International Electron Device Meeting, San Francisco, Calif. December, 1982 by N. Kamiya. Also, U.S. Pat. No. 4,114,255 describes the use of p-type regions formed as part of "front-end" processing which cause charge to be more easily injected from the channel into a floating gate device.